Imec and Cadence Tape Out Industry’s First 3nm Test Chip

Extreme ultraviolet and 193 immersion lithography technology and Cadence digital tools used to design 3nm CPU core

LEUVEN, Belgium & SAN JOSE, Calif.--()--The world-leading research and innovation hub in nanoelectronics and digital technologies, imec, and Cadence Design Systems, Inc. (NASDAQ: CDNS) today announced that its extensive, long-standing collaboration has resulted in the industry’s first 3nm test chip tapeout. The tapeout project, geared toward advancing 3nm chip design, was completed using extreme ultraviolet (EUV) and 193 immersion (193i) lithography-oriented design rules and the Cadence® Innovus Implementation System and Genus Synthesis Solution. Imec utilized a common industry 64-bit CPU for the test chip with a custom 3nm standard cell library and a TRIM metal flow, where the routing pitch was reduced to 21nm. Together, Cadence and imec have enabled the 3nm implementation flow to be fully validated in preparation for next-generation design innovation.

“Expanding upon the work we did with imec in 2015 on the industry’s first 5nm tapeout, we are achieving new milestones together with this new 3nm tapeout, which can transform the future of mobile designs at advanced nodes.”

The Cadence Innovus Implementation System is a massively parallel physical implementation system that enables engineers to deliver high-quality designs with optimal power, performance and area (PPA) targets while accelerating time to market. The Cadence Genus Synthesis Solution is a next-generation, high-capacity RTL synthesis and physical synthesis engine that addresses the latest FinFET process node requirements, improving RTL designer productivity by up to 10X. For more information on the Innovus Implementation System, please visit www.cadence.com/go/innovus3nm, and to learn about the Genus Synthesis Solution, visit www.cadence.com/go/genus3nm.

For the project, EUV and 193i lithography rules were tested to provide the required resolution, while providing PPA comparison under two different patterning assumptions. For more information on EUV technology and 193i technology, visit https://www.imec-int.com/en/articles/imec-presents-patterning-solutions-for-n5-equivalent-metal-layers.

“As process dimensions reduce to the 3nm node, interconnect variation becomes much more significant,” said An Steegen, executive vice president for semiconductor technology and systems at imec. “Our work on the test chip has enabled interconnect variation to be measured and improved and the 3nm manufacturing process to be validated. Also, the Cadence digital solutions offered everything needed for this 3nm implementation. Due to Cadence’s well-integrated flow, the solutions were easy to use, which helped our engineering team stay productive when developing the 3nm rule set.”

“Imec’s state-of-the-art infrastructure enables pre-production innovations ahead of industry demands, making them a critical partner for us in the EDA industry,” said Dr. Chin-Chi Teng, corporate vice president and general manager in the Digital & Signoff Group at Cadence. “Expanding upon the work we did with imec in 2015 on the industry’s first 5nm tapeout, we are achieving new milestones together with this new 3nm tapeout, which can transform the future of mobile designs at advanced nodes.”

About Cadence

Cadence enables electronic systems and semiconductor companies to create the innovative end products that are transforming the way people live, work and play. Cadence software, hardware and semiconductor IP are used by customers to deliver products to market faster. The company’s System Design Enablement strategy helps customers develop differentiated products—from chips to boards to systems—in mobile, consumer, cloud datacenter, automotive, aerospace, IoT, industrial and other market segments. Cadence is listed as one of Fortune Magazine's 100 Best Companies to Work For. Learn more at cadence.com.

About imec

Imec is the world-leading research and innovation hub in nanoelectronics and digital technologies. The combination of our widely acclaimed leadership in microchip technology and profound software and ICT expertise is what makes us unique. By leveraging our world-class infrastructure and local and global ecosystem of partners across a multitude of industries, we create groundbreaking innovation in application domains such as healthcare, smart cities and mobility, logistics and manufacturing, energy and education.

As a trusted partner for companies, start-ups and universities we bring together close to 3,500 brilliant minds from over 70 nationalities. Imec is headquartered in Leuven, Belgium and has distributed R&D groups at a number of Flemish universities, in the Netherlands, Taiwan, USA, China, and offices in India and Japan. In 2016, imec's revenue (P&L) totaled 496 million euro. Further information on imec can be found at www.imec-int.com.

© 2018 Cadence Design Systems, Inc. All rights reserved worldwide. Cadence, the Cadence logo and the other Cadence marks found at www.cadence.com/go/trademarks are trademarks or registered trademarks of Cadence Design Systems, Inc. All other trademarks are the property of their respective owners.

Imec is a registered trademark for the activities of IMEC International (a legal entity set up under Belgian law as a "stichting van openbaar nut”), imec Belgium (IMEC vzw supported by the Flemish Government), imec the Netherlands (Stichting IMEC Nederland, part of Holst Centre which is supported by the Dutch Government), imec Taiwan (IMEC Taiwan Co.) and imec China (IMEC Microelectronics (Shanghai) Co. Ltd.) and imec India (Imec India Private Limited), imec Florida (IMEC USA nanoelectronics design center).

Contacts

Cadence Newsroom
408-944-7039
newsroom@cadence.com
or
imec:
Hanne Degans, Office: +32 16 28 17 69
press communications manager
Hanne.Degans@imec.be
Mobile: +32 486 06 51 75

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Release Summary

Imec and Cadence tape out the industry’s first 3nm test chip.

Cadence Design Systems, Inc.