HENDERSON, Nev.--(EON: Enhanced Online News)--Aldec, Inc., today announced the immediate availability of Active-HDL™ version 9.3, introducing a revolutionary approach to the increasing challenges of global project management. “Today’s complex FPGA devices are designed with multiple teams and require more efficient team-based project management tools,” said Satyam Jani, Aldec Software Division Product Manager. “This release of Active-HDL has made substantial strides in managing tool settings for multi-design FPGA projects and team-based environments.”
“Today’s complex FPGA devices are designed with multiple teams and require more efficient team-based project management tools”
New Project Management Features
- Active-HDL’s user-defined directory structure allows engineers to create project structures compatible with standard Synthesis and Place & Route tools, allowing one common project structure to be used between multiple vendor tools.
- Multi-design projects involve many settings, for example: setting a working directory, updating local variables, setting a script mode, executing specific macros, etc. Active-HDL 9.3 introduces a load-time setup file approach that automatically loads these settings.
- After initial set-up, the simulator can be set at different running modes with a single click. This feature allows users to run Active-HDL in the right mode for each task; Optimized mode will run the simulator at the highest possible speed while Debug and Coverage mode will run at reduced speed while collecting data for later analysis.
Award-winning Active-HDL, an FPGA designer tool-of-choice for over 15 years, is an HDL-based FPGA Design and Simulation solution that offers design creation, documentation, code coverage and simulation in one tightly integrated environment.
- Team-based design management to manage complex FPGA projects easily
- High-performance mixed language support with VHDL 2008, Verilog and SystemVerilog(Design) support
- Pre-compiled libraries for latest FPGA devices from Altera®, Lattice®, Microsemi™ (Actel) and Xilinx®
- Floating point support in Waveform Viewer
New customers and customers without current maintenance contracts are invited to contact their local Aldec Distributor to receive additional information on the latest release.
For additional information about Active-HDL 9.3 including tutorials, free evaluation downloads and What’s New Presentation, please visit http://www.aldec.com/Products/Active-HDL.
Aldec Inc., headquartered in Henderson, Nevada, is an industry leader in Electronic Design Verification and offers a patented technology suite including: RTL Design, RTL Simulators, Hardware-Assisted Verification, SoC and ASIC Prototyping, Design Rule Checking, IP Cores, Requirements Lifecycle Management, DO-254 Functional Verification and Military/Aerospace solutions. www.aldec.com
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