Oasys Design Systems Has Breakout Year in 2012

Cash Flow Positive Q4 Based on 114% Orders Growth Sets Stage for 2013

SANTA CLARA, Calif.--()--Oasys Design Systems, providers of a revolutionary new platform for RTL synthesis that empowers RTL engineers, announced today that orders more than doubled in 2012 by the addition of several of the top semiconductor and IP vendors to its previous list of marquee customers. Oasys orders increased at an accelerated rate throughout 2012 as companies designing SoCs and ASICs continued to transition to advanced process nodes and novel device structures such as FinFETs, further stressing the capacity of their existing, traditional block-level synthesis tools. Oasys ended 2012 with a cash flow positive fourth quarter that sets the stage for continued growth in momentum in 2013.

“RTL engineers are realizing that the RTL handoff design flow at 28 nm and below requires using a physically aware synthesis tool with greatly increased design capacity to avoid unexpected iterations late in the design cycle that delays their time to market”

“RTL engineers are realizing that the RTL handoff design flow at 28 nm and below requires using a physically aware synthesis tool with greatly increased design capacity to avoid unexpected iterations late in the design cycle that delays their time to market," said Scott Seaton, Oasys President and CEO. “The Oasys RealTime synthesis engine optimizes at a higher level of abstraction, providing massive synthesis capacity and breakthrough runtime performance for today’s complex SoC and ASIC designs. RealTime synthesis was production proven in 2012 at the 28nm node by several customers and we’re now working closely with them, and our new customers, on 20nm and 14nm RTL design flows.”

Oasys recently introduced a new RTL exploration tool, RealTime Explorer, allowing RTL engineers to quickly and accurately identify top-level timing, power, area, and routing issues in their RTL before handoff to physical design teams. No other synthesis vendor offers the capacity to optimize the top-level of today’s complex designs that literally contain 100s of millions of gates, in one synthesis run. Oasys customers have demonstrated that with the Oasys high capacity and physically aware synthesis tool, unexpected iterations that delay design closure can be avoided.

RealTime Explorer is built upon the identical synthesis engine as the Oasys RealTime Designer tool that was introduced in 2009. For the first time, RTL engineers are guaranteed that the results they see during RTL exploration are exactly the same results that can be implemented by their physical design teams. “Our customers are taking advantage of the unique logical-to-physical cross probing capability of the unified RealTime database to resolve top-level timing and routing issues early in the design cycle – with the confidence of knowing the results will be achievable in a single iteration during the critical placement and routing process,” said Paul van Besouw, CTO and founder of Oasys.

About Oasys Design Systems

Oasys Design Systems is a privately funded electronic design automation (EDA) software supplier with a revolutionary new synthesis platform called RealTime, a fundamental shift in how RTL synthesis is used to design and implement today’s SoCs and ASICs. Corporate headquarters is located at 3250 Olcott Street, Suite 105, Santa Clara, Calif. 95054. Telephone: (408) 855-8531. Facsimile: (408) 855-8537. Email: info@oasys-ds.com. For more information, visit: www.oasys-ds.com.

RealTime, RealTime Designer and RealTime Explorer are trademarks of Oasys Design Systems. All other trademarks and registered trademarks are the property of their respective owners.

Contacts

Oasys Design Systems
Dan Ganousis, 303-859-3048
Vice President, Sales and Marketing
dganousis@oasys-ds.com