SANTA CLARA, Calif.--(BUSINESS WIRE)--Oasys Design Systems, the chip synthesis company, announced today that industry veteran Scott Seaton has been named the company’s President and CEO. Mr. Seaton was also appointed a director of the company. Mr. Seaton succeeds founder Paul van Besouw who will become the company’s CTO and Chairman of its board of directors.
“I am excited about the dramatic value in time-to-market savings our customers are seeing with Oasys RealTime Designer over their existing RTL synthesis tools”
“Oasys RealTime Designer’s massive RTL capacity and breakthrough performance enables optimization at the top level of today’s most complex designs which allows designers to find timing, power, area, and routability problems before physical design. The result is a dramatic reduction in design iterations for design closure, providing important time-to-market savings over existing synthesis tools that are limited to block-level optimization. Oasys RealTime Designer is in production use at several of the top 10 semiconductor firms and our customers have successfully taped out designs at the 28nm process node,” said van Besouw. “Scott’s extensive EDA business experience taking start-up companies to the next level will help Oasys scale and lead us into our next phase of growth.”
Mr. Seaton is an EDA veteran with more than 30 years of experience in sales, marketing and executive management. Most recently Mr. Seaton was VP of Sales and Marketing at Carbon Design Systems where he helped transform the company into a market leader in system level design. Previously, Mr. Seaton was the VP of Worldwide Sales at Enkoo, an SSL VPN networking appliance company that was acquired by Sonicwall. Earlier Mr. Seaton was President and CEO of LIstenpoint, a venture-backed enterprise software company. Mr. Seaton began his EDA career as VP of Channel Sales at Viewlogic.
“I am excited about the dramatic value in time-to-market savings our customers are seeing with Oasys RealTime Designer over their existing RTL synthesis tools,” stated Mr. Seaton. “As Moore’s law continues to enable ever more complex designs, customers are finding that their existing RTL design flows, built upon RTL synthesis technology that was architected 25 years ago, can no longer solve their timing, power, area, and routability problems. This creates a great opportunity for Oasys to leverage its breakthrough optimization and physical synthesis technology.”
About Oasys Design Systems
Oasys Design Systems is a privately funded electronic design automation (EDA) software supplier with a revolutionary new platform called Chip Synthesis™, a fundamental shift in how RTL synthesis is used to design and implement today’s SoCs and ASICs. Corporate Headquarters is located at 3250 Olcott Street, Suite 105, Santa Clara, Calif. 95054. Telephone: (408) 855-8531. Facsimile: (408) 855- 8537. Email: firstname.lastname@example.org. For more information, visit: www.oasys-ds.com.
RealTime Designer and Chip Synthesis are trademarks of Oasys Design Systems. All other trademarks and registered trademarks are the property of their respective owners.