DVCon U.S. 2017 Announces Advance Program; Registration is Open

LOUISVILLE, Colo.--()--The 2017 Design and Verification Conference and Exhibition U.S. (DVCon) Advance Program is now available online and registration is open. DVCon U.S., sponsored by Accellera Systems Initiative, will be held February 27-March 2, 2017 at the DoubleTree Hotel in San Jose, California.

“Practicing design and verification engineers, managers and EDA tool suppliers have come to depend on DVCon for content that not only looks to the future, but discusses issues and solutions that are helpful in their daily jobs”

“Practicing design and verification engineers, managers and EDA tool suppliers have come to depend on DVCon for content that not only looks to the future, but discusses issues and solutions that are helpful in their daily jobs,” stated Dennis Brophy, DVCon U.S. 2017 general chair. “Our Technical Program Committee has done an outstanding job to review and choose meaningful program content from the many excellent contributions they received this year. Attendees can look forward to a compelling and in-depth technical program full of engaging topics that continue the tradition of DVCon as a must-attend conference.”

Accellera Day kicks off the conference on Monday, February 27 and will include one morning tutorial, “Creating Portable Stimulus Models with the Upcoming Accellera Standard,” and two afternoon tutorials, "SystemC Design and Verification – Solidifying the Abstraction above RTL" and "Introducing IEEE P1800.2 – The Next Step for UVM." There will also be a luncheon that will include the presentation of Accellera’s annual Technical Excellence Award. The DVCon Expo and Booth Crawl will follow the tutorials at 5:00pm.

The Keynote will be given this year by Anirudh Devgan, Senior Vice President and General Manager of the Digital & Signoff Group and System & Verification Group with Cadence Design Systems, on Tuesday, February 28 at 1:30pm. There will also be a special session at 10:30am on Tuesday, “Trends in Functional Verification: A 2016 Industry Study.” Two panel sessions will be held on Wednesday, March 1: “User’s Talk Back on Portable Stimulus” at 8:30am and “SystemVerilog Jinxed Half My Career: where do we go from here?” at 1:30pm. Attendees can choose from 39 papers, 9 tutorials and approximately 19 poster sessions over the course of the 4-day technical conference and exhibition.

Attendees will have many opportunities for networking during DVCon U.S. The 3-day Expo with a booth Crawl on Monday evening and the Exhibits Reception on both Tuesday and Wednesday evening provide excellent opportunities to connect with peers and industry experts.

For the complete DVCon U.S. 2017 schedule, including a list of sessions, tutorials, sponsored luncheons and events, visit www.dvcon.org. To view the videos from the DVCon U.S. 2016 tutorials, visit http://www.accellera.org/resources/videos/.

DVCon is the premier conference for discussion of the functional design and verification of electronic systems. DVCon is sponsored by Accellera Systems Initiative, an independent, not-for-profit organization dedicated to creating design and verification standards required by systems, semiconductor, intellectual property (IP) and electronic design automation (EDA) companies. In response to global interest, in addition to DVCon U.S., Accellera also sponsors DVCon China, DVCon Europe and DVCon India. For more information about Accellera, please visit www.accellera.org. For more information about DVCon U.S., please visit www.dvcon.org. Follow DVCon on Facebook https://www.facebook.com/DvCon or @dvcon_us on Twitter or to comment, please use #dvcon_us.

Contacts

MP Associates, Inc.
Nannette Jordan, 303-530-4562
nannette@mpassociates.com
or
HighPointe Communications
Barbara Benjamin, 503-209-2323
barbara@hipcom.com

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